Design parameters for an integrated circuit may vary wafer lot to waver lot, from wafer to wafer within lot, from die to die on a wafer, and within die of an integrated circuit.
Referring now to background FIG. 1A, a wafer 100 is illustrated with a plurality of integrated circuit die 102A-102N formed therein in a matrix or rows and columns. FIG. 1A further illustrates a hierarchy of circuitry that may be used to define an integrated circuit die 102A. Each complete integrated circuit (“full chip”) die 102A may include macro functional blocks 104 as well as lower level blocks and circuit cells. The macro functional blocks 104 for example may be processors, memory, or other types of functional blocks. The macro functional blocks 104 may be made of other smaller functional blocks 106 grouped together. The functional blocks 106, for example, may be registers, ALUs, control logic, random logic, or other types of functional blocks. The functional blocks 106 may be formed out of standard circuit cells 108 from a standard cell library.
A standard cell library typically includes a wide variety of types of standard circuit cells that provides basic low level functionality such as logic gates (e.g., AND, OR, XOR, INVERT, NAND, NOR, XNOR, BUFFER; multiplexer); basic storage logic (e.g., latch, flip flop, register, memory cell); input receivers, output drivers, and input/output buffers; tristate drivers; counters; etc. that are typically associated with an integrated circuit design. For each standard circuit cell in the standard cell library, information is provided regarding the cell dimensions, layers utilized, pin locations and layer, routing layers, and timing/delay information in a format that is known and read/writeable by IC CAD tools.
At a lowest level of an IC design and netlist are the active and passive electronic devices, such as transistors, resistors, and capacitors. Resistors and capacitors may be parasitic devices that were not intended to be a part of the design but are the result from manufacturing the semiconductor integrated circuit. One or more transistors 110 may be used to form a standard circuit cell 108.
A plurality of the one or more standard circuit cells 108 may be used to form a functional block 106. For example, a set of sixteen D-type flip flop standard cells may be placed parallel to each other with control signals interconnected to form a sixteen bit register functional block. Alternatively, a mixture of types of standard circuit cells 108 may be combined to form a functional block. For example, a two bit adder may be formed of a combination of NAND, NOR, and INVERT standard cell circuits.
Variation or uncertainty in a semiconductor integrated circuit may result from the matrix (row and column) position of an integrated circuit on the wafer. For example, the performance of integrated circuit 102B near the center of the wafer 100 may differ from the performance of integrated circuit 102A nearer the edge of the wafer 100. This may be referred to as a chip-to-chip or die-to-die variation.
Variation or uncertainty in a semiconductor integrated circuit may also be a function of location within the integrated circuit die itself. For example, circuits that are placed near an edge of the integrated circuit die may have more defects and lower yield than circuits placed near the center of a die. As another example, a circuit placed in a crowded area of an integrated circuit may experience greater heating and provide lower performance than a circuit well spaced apart with a lower level of heating and a better performance. Variation that is found within the integrated circuit itself to vary may be categorized as being an intra-chip or within-die variation. Intra-chip or within-die variation may be different at different locations of the same integrated circuit chip.
Referring now to background FIG. 1B, a pair of manufacturing lots 140A-140B of wafers with the same integrated circuit design manufactured in a plurality of matrix positions is illustrated. Lot 140A includes N wafers 100A-100N. Lot 140B includes M wafers 100A′-100M′.
In addition to the matrix position, the uncertainty in the performance of an integrated circuit may vary from wafer to wafer and from manufacturing lot to lot. For example, the performance of integrated circuit 102C on wafer 100A may differ from the performance of a similar integrated circuit 102D on wafer 100B even though they are in the same matrix position (same row, column position) on each. For example, the performance of integrated circuit 102C on wafer 100A in Lot 140A may differ from the performance of integrated circuit 102E on wafer 100A′ in Lot 140B even though they are in the same matrix position (same row, column position) on each wafer. It may be the case that the performance of integrated circuit 102F on wafer 100B′ will differ more from the performance of integrated circuit 102E on wafer 100A′ because they are at different matrix positions and on different wafers.
The size of each fabricated geometry on a semiconductor IC depends on the local lithographic and etching environment.
A circuit cell may be placed horizontally or vertically within an integrated circuit with respect to the manufactured wafer. Because of the details of mask making technology, and optical exposures, this may cause a systematic channel length (L) dependence as a function of the cells orientation—horizontal or vertical.
The thickness of the metal and dielectric layers depends on the local chemical mechanical planarization (CMP) environment. A chemical mechanical planarization may be performed on one or more metal layers and the metal lines formed therein and/or dielectric layers reducing their thicknesses. A thinner metal signal line may generate a greater parasitic resistance and slow down signal transmission. A thinner metal power line may reduce its current carrying capabilities and result in a power failure. A thinner dielectric layer may result in increased parasitic capacitance between metal layers and the metal lines formed therein and reduce the speed of signal transmission.
Device and interconnect sizes may also depend on where in the optical field the device lies on the integrated circuit (an intra-chip or within-die variation).
Deposition and etching steps typically vary across a wafer's surface. Even with real time control, the thickness of a feature may only be exactly correct at one spot of a wafer.
Referring now to background FIG. 1C, the integrated circuit design 152 is manufactured into silicon chips or die 102 across lots of wafers 100 in a manufacturing facility 150A-150B that may be referred to as a wafer fab or fab. The fab 150A-150A in which the chip will be built may be unknown, and perhaps not yet constructed. Even if pre-existing, the wafer fab manufacturing performance and statistics may be time varying, such as from lot to lot or from wafer to wafer. Additionally, the IC design 152 may be manufactured in differing fabs 150A-150B so that the performance or the IC varies from fab to fab.
With the same IC design netlist 152 for the integrated circuit, differing standard cell libraries 154A-154B may be used and provide performance variations. Even if the same standard cell library is used with the same IC design netlist 152, manufacturing differences in the fabs 150A-150B can cause variations in the performance of the integrated circuits 102G-102H manufactured in each of the respective wafers 100X-100Y.
With shrinking sizes, the inherent effect of process variations is playing a larger factor in defining the behavior of a circuit. Modeling the effects of process variations in the design stage of a circuit may improve its yield during manufacturing and its performance during operation.